1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to a method of performing a self-aligned silicide process using a titanium layer with an overlying titanium nitride barrier layer to prevent nitridation of the titanium layer during the first rapid thermal anneal step, thereby reducing the sheet resistance of the N+ source and drain regions and the N+ polysilicon.
2) Description of the Prior Art
The use of self-aligned silicide (SALICIDE) processes has resulted in higher performing, lower cost, and increased density semiconductor devices. However, sheet resistance (Rs) at the salicide interface is a key limitation of current SALICIDE processes, particularly as processing speed increases.
In current SALICIDE processes, a titanium layer is deposited over a gate and adjacent source and drain regions. The substrate is then exposed to a rapid thermal anneal (RTA) in which the titanium in areas that overlie silicon (i.e. gate electrode and source and drain regions) reacts with the silicon to form titanium silicide, and the titanium in areas that do not overlie silicon (i.e. nitride or oxide spacers and isolation structures) the titanium does not react. Unreacted titanium is then removed using a selective metal etch. Then a second RTA is performed to further lower the sheet resistance of the silicide.
The RTA steps are performed in a nitrogen containing atmosphere. During the first RTA step, the nitrogen reacts with the titanium at the surface of the titanium layer forming titanium nitride. Thus, the titanium which reacts with nitrogen is not available to form titanium silicide, and the titanium nitride prevents subsequent ion mixing step from effectively reducing the sheet resistance at the silicide interface.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 4,835,112 (Pfiester et al.) shows a salicide process using a Ge ion implant.
U.S. Pat. No. 4,551,908 (Nagasawa et al.) recites a salicide process with an ion mixing step.
U.S. Pat. No. 5,789,318 (Delfino et al.) shows a salicide process using a sputter deposited TiH.sub.x.ltoreq.2 which is converted to C-49 TiSi.sub.2 and TiN during a first rapid thermal anneal.